Delay lines are used in clock management blocks of integrated circuit (IC) devices, such as field programmable gate arrays (FPGAs), to control timing of various signals therein. A simple delay line receives an input signal on an input terminal and provides an output signal on an output terminal, where the output signal is delayed by a certain time period that is referred to as delay, D, of the delay line.
An IC device such as an FPGA can use a delay line in a digital clock management (DCM) block to synchronize clock signals. Delay lines typically comprise a number of delay elements and may be, for example, voltage controlled or tap-controlled. In tap-controlled delay lines, the delay elements are commonly referred to as “taps.”
In DCM circuits, excess jitter and power dissipation in a delay line can deleteriously affect performance of the circuit. Power dissipation in a delay line is a function of switching activity. One contributing factor to jitter in single-ended delay lines is power supply noise (including GND bounce). Jitter in a delay line increases proportionally with power supply noise. Power supply noise is proportional to the time derivative of the instantaneous current i(t) drawn from the power supply d(i)/dt. Thus, high-frequency current changes on the power supply of the delay line increase jitter. While circuits exist to protect delay lines from external noise sources, little attention has been given to local noise sources generated by running taps in tap-controlled delay lines and their corresponding circuits.
Accordingly, it would be both desirable and useful to provide method and apparatus for reducing jitter and power dissipation in a delay line.